In the manufacture of semiconductor chip devices, photolithographic processes are often used to pattern various layers on a wafer in order to produce circuit features (e.g., transistors, polygates and interconnects) positioned as specified in a circuit feature layout. Typically, a circuit feature layout calls for different circuit features to be provided in different layers and/or through different combinations of layers of the chip devices. Examples of circuit feature layouts which include such circuit features positioned in such relationships are numerous. An example of a device having such a circuit feature layout is one which includes multiple layers, at least one of the layers having one or more conductive paths (e.g., digitlines), and at least one interconnect passing through two or more of the layers but not making contact with the conductive path(s). In manufacturing such a device, it is common to form the one or more conductive paths by patterning a conductive layer in one photolithographic patterning step, and subsequently (e.g., after applying one or more layers over the conductive layer) to form the interconnect(s) using a separate photolithographic patterning step.
In each of such photolithographic processes, a layer of photo resist is deposited on the layer being patterned, and the resist is then exposed using an exposure tool and a template. These templates are known in the art as reticles or masks. For purposes of the present application, the term reticle includes both reticles and masks. During the exposure process, the reticle is typically placed over the resist, and then a form of radiant energy such as ultraviolet light is directed toward the reticle to selectively expose the resist in a desired pattern. A preferred device for creating such exposure is known as a stepper.
In performing such photolithographic processes on a device which is being manufactured, it is necessary to align each reticle relative to the device under fabrication. There are a number of ways of providing such alignment, one common way being to provide for accurate alignment of the device relative to the stepper, as well as accurate alignment of each reticle relative to the stepper. One common way of providing such accurate alignment is by providing alignment marks on the device, which can be aligned with corresponding marks on the stepper. Other alignment techniques could be used, e.g., positioning one or more edges of the device in contact with a mating surface in the stepper, registering a notch in the edge of the device with an engaging structure in the stepper, registering a hole in the device with an engaging structure in the stepper, etc. Likewise, each reticle is accurately aligned with the stepper using a suitable alignment technique. In practice, such alignment can only be guaranteed within certain limits. Accordingly, different reticles used in different steps in the manufacture of a semiconductor device can be misaligned up to a maximum amount referred to herein as the alignment budget therefore the alignment errors will produce defective product.
One type of reticle which is commonly used in photolithographic processes is referred to as a binary reticle. A binary reticle includes reticle features, namely transparent features (areas through which exposure passes) and opaque features (areas which block exposure). The design of the reticle features is typically shown in a two-dimensional reticle layout, although the reticle itself typically includes two or more layers (e.g., a transparent layer and a patterned opaque layer). In use, radiant energy is directed toward the binary reticle, and the radiant energy is blocked by the opaque areas but passes through the transparent areas to pattern-wise expose the resist. After pattern-wise exposure, the resist is developed to remove either the exposed portions of the resist (a positive resist) or the unexposed portions of the resist (a negative resist), thereby forming a patterned resist on the layer being patterned. The patterned resist is then used to protect a corresponding pattern of underlying areas on the layer during subsequent fabrication processes, such as deposition, etching or ion implantation processes. Thus, the patterned resist prevents or substantially prevents the effects of the fabrication process(es) from being produced in the layer in areas of the layer which lie beneath portions of the resist which have not been removed. The reticle is designed so as to enable exposing the resist in a pattern which corresponds to the feature or features which are desired to be formed.
There are a number of effects caused by diffraction of exposure which tend to distort the patterns formed in a resist, i.e., which cause the pattern formed in a resist to differ from the pattern formed in the reticle.
Due to limitations imposed by the wavelength of light used to transfer the pattern, resolution degrades at the edges of the patterns of the reticle. Such degradation is caused by diffraction of the exposure such that it is spread outside the transparent areas. Phase shift masks (PSMs) have been used to counteract these diffraction effects and to improve the resolution and depth of images projected onto a target (i.e., the resist covered wafer). There are a variety of PSMs. One kind of PSM includes a phase shifting layer having areas which allow close to 100% of the exposure to pass through, but phase shifted 180 degrees relative to exposure passing through a transparent layer. Attenuated PSMs utilize partially transmissive regions which pass a portion of the exposure, e.g., about three to eight percent, out of phase with exposure through transparent areas. Typically, the shift in phase is 180 degrees, such that the portion of exposure passing through the partially transmissive regions destructively interferes with exposure which is spread outside the transparent areas by diffraction. Phase shift masks can thereby increase image contrast and resolution without reducing wavelength or increasing numerical aperture. These masks can also improve depth of focus and process latitude for a given feature size. Designs of such reticles typically are represented using one or more two-dimensional reticle layouts including appropriate reticle features, e.g., selected from among transparent features, opaque features, phase shifting features and phase shifting attenuating features.
There has been an ongoing need to increase the density of features contained in semiconductor devices, by making the features smaller and/or reducing the amount of space between features. Advances in feature density have required that reticles include correspondingly smaller and/or more densely packed features. The extent to which features printed by photolithographic methods can be reduced in size is limited by the resolution limit of the exposure tool. The resolution limit of an exposure tool is defined as the minimum feature dimension that the exposure tool can repeatedly expose onto the resist, and is a function of the wavelength of exposure emitted by the stepper, the aperture through which exposure is emitted, the depth of focus and other factors. Thus, reticle design is limited in that the gaps between respective features on the reticle (i.e., transparent regions, opaque regions and/or phase shifted regions) must be large enough for the circuit features to be correctly printed.
The critical dimension (CD) of a circuit pattern is defined as the smallest width of a line in the pattern, or the smallest space between lines in the pattern. The CD thus directly affects the size and density of the design. As the density of features in a pattern is increased, the CD of the design approaches the resolution limit of the stepper. As the CD of a circuit layout approaches the resolution limit of the stepper, the diffraction of exposure causes increasingly significant distortions of the pattern being created.
These distortions are known as optical proximity effects. The primary optical proximity effects are that corners of features are rounded, isolated features print differently from identically shaped and sized semi-isolated or densely packed features, smaller features are printed relatively smaller than larger features, and relatively thin line features are shortened. Features which are in close proximity to other features tend to be more significantly distorted than features which are relatively isolated from other features. Furthermore, optical proximity effect distortion is compounded by subsequent processing step distortions such as resist processing distortions and etching distortions.
As a result, many accuracy-enhancing design techniques have been developed, with the goal being to reduce such distortion by creating a modified reticle layout. Such techniques include those referred to in the art as optical proximity correction (OPC) techniques, and involve generating an initial reticle layout corresponding to features in the circuit feature layout, and adding and/or subtracting areas to the initial reticle layout to produce a modified reticle layout. The additions and/or subtractions are designed such that the pattern formed by exposure through the modified reticle layout will more closely correspond to the desired pattern. Typically, OPC is performed by using software which evaluates a digital representation of an initial reticle layout to identify regions where distortion will occur, and to modify the sizes and/or shapes of the elements in the initial reticle layout to produce the modified reticle layout. However, the expression OPC, as used in the present specification refers to any modification of a shape corresponding to a feature, e.g., modifications generated by known software routines, modifications made manually by the manufacturer (such as by trial and error) and modifications made by software routines not known in the art.
U.S. Pat. No. 5,821,014 discloses a method comprising using scattering bars between features for correcting for proximity effects. According to the patent, scattering bars are correction features (typically non-resolvable) that are placed next to isolated edges on a mask in order to adjust the edge intensity at the isolated edge to match the edge intensity at a densely packed edge.
U.S. Pat. No. 5,723,233 discloses an optical proximity correction method for mask layouts. The method includes performing pattern recognition on a layout design to identify locations of feature edges with respect to other feature edges in the layout design. The method further includes obtaining an optical proximity correction for at least one of the feature edges by evaluating one or more non-linear mathematical expressions for optical proximity correction at the location of that edge with respect to other feature edges.
U.S. Pat. No. 5,707,765 discloses a method of making a photolithography mask that utilizes serifs to increase the correspondence between an actual circuit design and the final circuit pattern on a semiconductor wafer. The mask uses a plurality of serifs having a size determined by a resolution limit of the optical exposure tool used during the fabrication process. The serifs are positioned on the corner regions of the mask such that a portion of surface area for each of the serifs overlaps the corner regions of the mask. The size of the serifs is about one-third the resolution limit of the optical exposure tool.
After conducting an initial OPC, the modified reticle layout is preferably checked to analyze differences between the pattern that will be produced on a resist (the printed circuit pattern) and the desired circuit feature layout. Depending on these differences, additional modifications can be made to the modified reticle layout, which may include changes to one or more of the features in the modified reticle layout.
When manufacture of a semiconductor device requires more than one photolithographic process, as described above and as is typically the case, the device being manufactured and each of the reticles are aligned relative to one another within specific alignment budgets. Known OPC methods do not take such alignment budgets into account. As the features in circuit feature layouts are more densely packed, there is an increasingly larger chance that features which are designed to be electrically insulated from one another will be in contact with one another due to the alignment budgets.
In addition, after patterning a resist, processing steps are taken, e.g., etching, material deposition, etc., in order to form the circuit features in accordance with the pattern formed in the resist. In carrying out such processing steps, there typically is introduced further deviation from the original design of the features. The maximum extent of such deviations are referred to herein as processing budgets.
There is an ongoing need for methods of designing reticles which can be used to form features which are packed in patterns which are increasingly more dense, while reducing or eliminating printing errors and decreasing the variance between the actual exposure pattern and the desired exposure pattern. In addition, there is a need for methods of designing such reticles in which alignment budgets are taken into account. Furthermore, there is a need for such methods in which processing budgets are also taken into account.